feat: fixes and configuration to path
This commit is contained in:
Saleh Bubshait
@@ -5,7 +5,7 @@
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"Problem": "Implement a Verilog module that computes the parity of an 8-bit input vector. The output should be 1 if the number of '1's in the input is odd, and 0 otherwise.",
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"Module header": "module parity_8bit (\n input [7:0] in,\n output out\n);",
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"Testbench": "`timescale 1ns / 1ps\n\nmodule parity_8bit_tb;\n\n reg [7:0] test_in; // Input signal\n wire test_out; // Output signal\n reg expected_out; // Expected output for verification\n integer errors = 0; // Error counter\n\n // Instantiate the module under test\n parity_8bit uut (\n .in(test_in),\n .out(test_out)\n );\n\n integer i;\n reg [7:0] test_vectors[0:4]; // Test cases\n reg expected_values[0:4]; // Expected results\n\n initial begin\n // Define test cases and expected results\n test_vectors[0] = 8'b00000000; expected_values[0] = 0; // Even parity (0 ones)\n test_vectors[1] = 8'b11111111; expected_values[1] = 0; // Even parity (8 ones)\n test_vectors[2] = 8'b00000001; expected_values[2] = 1; // Odd parity (1 one)\n test_vectors[3] = 8'b10000000; expected_values[3] = 1; // Odd parity (1 one)\n test_vectors[4] = 8'b01010101; expected_values[4] = 0; // Even parity (4 ones)\n\n $display(\"==========Testbench results==========\");\n $display(\"=====================================\");\n $display(\" Test Input | Expected | Output | Pass/Fail \");\n $display(\"-------------------------------------\");\n\n for (i = 0; i < 5; i = i + 1) begin\n test_in = test_vectors[i];\n expected_out = expected_values[i];\n #10; // Wait for the output to stabilize\n\n if (test_out === expected_out) begin\n $display(\" %b | %b | %b | PASS\", test_in, expected_out, test_out);\n end else begin\n $display(\" %b | %b | %b | FAIL\", test_in, expected_out, test_out);\n errors = errors + 1;\n end\n end\n\n $display(\"=====================================\");\n if (errors == 0)\n $display(\"All tests passed\");\n else\n $display(\"Some tests failed\");\n\n $finish;\n end\n\nendmodule\n"
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},
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},
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"module": "mux4to1",
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"Problem": "Design a Verilog module that implements a 4-to-1 multiplexer using only basic logic gates (AND, OR, NOT).",
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@@ -186,8 +186,8 @@
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"module": "pipelined_max_finder",
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"Problem": "Implement a pipelined module to find the maximum value in a stream of 8-bit integers over 4 clock cycles, so it takes four 8-bit inputs. Use a 2-stage pipeline for comparison and selection.",
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"Module header": "module pipelined_max_finder (\n input clk, rst,\n input [7:0] x0,x1,x2,x3,\n output reg [7:0] max_value\n);",
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"Problem": "Implement a pipelined module to find the maximum value in a stream of 8-bit integers over 4 clock cycles, so it takes four 8-bit inputs. Use a 2-stage pipeline for comparison and selection.",
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"Module header": "module pipelined_max_finder (\n input clk, rst,\n input [7:0] x0,x1,x2,x3,\n output reg [7:0] max_value\n);",
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"Testbench": "`timescale 1ns/1ps\nmodule pipelined_max_finder_tb;\n\n reg clk;\n reg rst;\n reg [7:0] x0, x1, x2, x3;\n wire [7:0] max_value;\n\n // Instantiate the Unit Under Test (UUT)\n pipelined_max_finder uut (\n .clk(clk),\n .rst(rst),\n .x0(x0),\n .x1(x1),\n .x2(x2),\n .x3(x3),\n .max_value(max_value)\n );\n\n // Clock generation: period = 10ns\n initial clk = 0;\n always #5 clk = ~clk;\n\n // Test case arrays (4 test cases)\n reg [7:0] test_x0 [0:3];\n reg [7:0] test_x1 [0:3];\n reg [7:0] test_x2 [0:3];\n reg [7:0] test_x3 [0:3];\n reg [7:0] expected [0:3];\n\n integer i;\n integer errors;\n\n initial begin\n errors = 0;\n // Initialize test vectors.\n // Test Case 0: {10, 20, 5, 15} -> Expected max = 20\n test_x0[0] = 8'd10; test_x1[0] = 8'd20; test_x2[0] = 8'd5; test_x3[0] = 8'd15; expected[0] = 8'd200;\n // Test Case 1: {100, 50, 200, 150} -> Expected max = 200\n test_x0[1] = 8'd100; test_x1[1] = 8'd50; test_x2[1] = 8'd200; test_x3[1] = 8'd150; expected[1] = 8'd0;\n // Test Case 2: {0, 0, 0, 0} -> Expected max = 0\n test_x0[2] = 8'd0; test_x1[2] = 8'd0; test_x2[2] = 8'd0; test_x3[2] = 8'd0; expected[2] = 8'd255;\n // Test Case 3: {255, 100, 200, 250} -> Expected max = 255\n test_x0[3] = 8'd255; test_x1[3] = 8'd100; test_x2[3] = 8'd200; test_x3[3] = 8'd250; expected[3] = 8'd255;\n\n // Apply reset.\n rst = 1;\n x0 = 8'd0; x1 = 8'd0; x2 = 8'd0; x3 = 8'd0;\n #12;\n rst = 0;\n\n // Apply the test vectors on successive clock cycles.\n for (i = 0; i < 4; i = i + 1) begin\n @(negedge clk);\n x0 <= test_x0[i];\n x1 <= test_x1[i];\n x2 <= test_x2[i];\n x3 <= test_x3[i];\n end\n\n // After applying test vectors, drive zeros to flush the pipeline.\n x0 = 8'd0; x1 = 8'd0; x2 = 8'd0; x3 = 8'd0;\n\n // Wait for 4 clock cycles to capture the outputs corresponding to the test cases.\n $display(\"==========Testbench results==========\");\n $display(\"=====================================\");\n $display(\" Test Input | Expected | Output | Pass/Fail \");\n $display(\"-------------------------------------\");\n for (i = 0; i < 4; i = i + 1) begin\n @(negedge clk);\n if (max_value === expected[i]) begin\n $display(\" %3d, %3d, %3d, %3d | %3d | %3d | PASS\", \n test_x0[i], test_x1[i], test_x2[i], test_x3[i], expected[i], max_value);\n end else begin\n $display(\" %3d, %3d, %3d, %3d | %3d | %3d | FAIL\", \n test_x0[i], test_x1[i], test_x2[i], test_x3[i], expected[i], max_value);\n errors = errors + 1;\n end\n end\n $display(\"=====================================\");\n if (errors == 0)\n $display(\"All tests passed\");\n else\n $display(\"Some tests failed\");\n $display(\"=====================================\");\n $finish;\n end\n\nendmodule"
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